Donald Thomas
Logic Design and Verification Using SystemVerilog (Revised)
Auteur(s) : Donald Thomas
Date de publication : 01-03-2016
Edition : CreateSpace Independent Publishing Platform
Type : Broche
SystemVerilog is a Hardware Description Language that enables designers to work at the higher levels of logic design abstractions that match the increased complexity of current day integrated circuit and field-programmable gate array (FPGA) designs.
The majority of the book assumes a basic background in logic design and software programming concepts.
It is directed at: students currently in an introductory logic design course that also teaches SystemVerilog, designers who want to update their skills from Verilog or VHDL, and students in VLSI design and advanced logic design courses that include verification as well as design topics.
The book starts with a tutorial introduction on hardware description languages and simulation.... Lire la suite
The majority of the book assumes a basic background in logic design and software programming concepts.
It is directed at: students currently in an introductory logic design course that also teaches SystemVerilog, designers who want to update their skills from Verilog or VHDL, and students in VLSI design and advanced logic design courses that include verification as well as design topics.
The book starts with a tutorial introduction on hardware description languages and simulation.... Lire la suite
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